Field Effect Transistors (FETs) of various types are widely used in analog and digital electronics to provide various switching and amplification functions. FETs are a type of transistor that relies on an electric field to control the conductivity of a channel that is formed in a semiconductor material. In particular, a typical FET will include gate, source, and drain nodes, wherein application of a voltage to the gate node will control the flow of current between the source and drain nodes.
In certain applications, FETs are connected in series, where the source of one transistor is connected to the drain of another. One such application has been set forth in commonly assigned U.S. patent application Ser. No. 11/532,725 filed Sep. 18, 2006, entitled HIGH LINEARITY WIDE DYNAMIC RANGE RADIO FREQUENCY ANTENNA SWITCH, now U.S. Pat. No. 7,459,988, which is incorporated herein by reference in its entirety. Without delving into the details of operation of the antenna switch, an antenna switch as provided in the above-referenced application is illustrated in FIG. 1. In general, the antenna switch provides a wide dynamic range of operation and includes multiple FETs T1-T6, which are connected in series. A control input, VCONTROL, is provided to enable or disable the antenna switch. The control input VCONTROL is distributed to the gates G of each of the FETs T1-T6 via resistors R0-R6.
As noted, the FETs T1-T6 are coupled in series between two input/output ports (I/O). As illustrated, the drain D of FET T1 is coupled to a first input/output port I/O, while the source S of FET T1 is coupled to a drain D of FET T2 at node N1. Similarly, the source S of FET T2 is coupled to a drain D of FET T3 at node N2; the source S of FET T3 is coupled to the drain D of FET T4 at node N3; the source S of FET T4 is coupled to the drain D of FET T5 at node N4; and the source S of FET T5 is coupled to the drain D of FET T6 at node N5. The source S of FET T6 is coupled to the second input/output port I/O.
Capacitors C1 and C2 provide self-biasing of the switch branch under large signal conditions, and thereby improve linearity. Notably, each of the nodes N1-N5 is coupled to a bias network made of resistors R7-R14. In operation, direct current (DC) bias signals are provided to each of these nodes N1-N6 to ensure that when the antenna switch is disabled, the input impedance presented to the input/output ports (I/O) remains stable.
Although the above design performs well, it is not space efficient. In particular, having to lay out six different FETs T1-T6 and provide access to the respective nodes N1-N5 for biasing when the antenna switch is disabled takes up a significant amount of space on the semiconductor module in which the antenna switch is implemented.
In certain applications, multiple-gate FETs can be used in place of multiple FETs that are connected in series. With reference to FIG. 2A, a dual-gate FET T7 has a drain D, source S, a first gate G1, and a second gate G2. This dual-gate configuration is equivalent to two single-gate FETs T8 and T9 connected in series. The FET T8 will include a single gate G1, a drain D and a source S. The FET T9 will include a single gate G2, a drain D, and a source S. The source S of FET T8 is coupled to the drain D of FET T9 at node N1. Notably, if node N1 needs to be connected to related circuitry, the dual-gate FET T7 may not be a substitute, as node N1 is generally not available or accessible.
As another example, the triple-gate FET T10 of FIG. 2B will include three gates, G1, G2, and G3, along with a drain D and a source S. This configuration is equivalent to three FETs T11-T13 connected in series. Each of the FETs T11-T13 will include a respective one of the gates G1-G3 and a corresponding drain D and source S. The source S of FET T11 is coupled to the drain D of FET T12 at node N1, and the source S of FET T12 is coupled to the drain D of FET T13 at node N2. Again, in an application where nodes N1 and N2 require bias, the equivalent triple-gate FET T10 is generally not available.
As such, if multiple-gate FETs are used to reduce the number of individual transistors in the antenna switch of FIG. 1, the biasing that is provided to the nodes N1-N5 would not be available. As illustrated in FIG. 3, the six FETs T1-T6 are replaced with two triple-gate FETs T14 and T15. Each of the FETs T14 and T15 will include three gates G1, G2, and G3, which are connected to the control network R0-R6. The drain D of FET T14 is coupled to the first input/output port I/O, while the source S of FET T15 is coupled to the second input/output port I/O. The source S of FET T14 is coupled to the drain D of FET T15 at node N1. However, node N1 may not be biased because there is no ability to provide the distributed bias as provided in FIG. 1 due to the inaccessibility of actual or virtual source-drain connections or nodes within the multiple-gate FET architectures. R15 provides a resistive path between the respective input/output ports I/O.
FIGS. 4-6 provide high level overviews of a typical cross-section of three different FET architectures. FIG. 4 depicts a dual-gate pseudomorphic high-electron mobility transistor (pHEMT), FIG. 5 depicts a dual-gate metal oxide semiconductor field-effect transistor (MOSFET), and FIG. 6 illustrates a dual-gate metal semiconductor field-effect transistor (MESFET).
With particular reference to FIG. 4, the transistor structure 10 for a dual-gate pHEMT will include a source 12, drain 14, first gate 16, second gate 18, and an inner source-drain (SD) node 20. The first and second gates 16, 18 are located between the source 12 and the drain 14. The inner SD node 20 has a similar semiconductor structure as that of the source 12 and drain 14, and is located between the first gate 16 and the second gate 18. The various transistor elements are generally formed on a given substrate 22. In this example, an indium gallium arsenide (InGaAs) channel layer 24 resides on the substrate 22, and an aluminum gallium arsenide (AlGaAs) schottky layer 26 resides on the InGaAs channel layer 24. To form the source 12, an etch stop material is formed over a source area, and a gallium arsenide (GaAs) cap section 30 that is heavily doped (N+) with N-type material is provided over the etch stop section 28. A source ohmic metal contact 32 is provided over the GaAs cap layer 30 to facilitate electrical connection to the source 12. The drain 14 is formed in a similar fashion. An etch stop section 34 is left over the drain area, and a GaAs cap section 36 that is heavily doped (N+) with N-type material is provided over the etch stop section 34. A drain ohmic metal 38 is provided over all or a portion of the GaAs cap section 36 to facilitate electrical connection to the drain 14.
The inner SD node 20, from a semiconducting perspective, looks the same or similar to the source 12 and drain 14, with the exception of the source ohmic metal 32 and the drain ohmic metal 38. As such, the inner SD node 20 may include an etch stop section 40 over an area forming the inner SD node 20, where a corresponding GaAs cap section 42 that is heavily doped (N+) with N-type material is formed over the etch stop section 40. There is no ohmic metal layer on top of the GaAs cap section 42 of the inner SD node 20. A first gate metal section 44 is applied on the schottky layer 26 between the source 12 and the inner SD node 20 to form the first gate 16. Similarly, a second gate metal section 46 is applied on the schottky layer 26 between the inner SD node 20 and the drain 14 to form the second gate 18. A dielectric or passivation layer 48 may be applied over most or all of the transistor architecture, with the exception of a portion of the source ohmic metal 32 and a portion of the drain ohmic metal 38 to finalize fabrication.
Turning to FIG. 5, a transistor structure 10 of a dual-gate MOSFET is provided. The basic structure is the same as that of the pHEMT of FIG. 4, with the exception that a first gate insulator 50 is used to insulate the first gate metal section 44 from the schottky layer 26, and a second gate insulator 52 is used to insulate the second gate metal 46 from the schottky layer 26. The source 12, drain 14, and inner SD node 20 are configured in a similar fashion to the pHEMT of FIG. 4.
With reference to FIG. 6, the transistor structure 10 of a dual-gate MESFET is provided. The dual-gate MESFET is formed in a semi-insulating GaAs substrate 22. Different sections of the substrate 22 are either heavily doped (N+) or lightly doped (N−) with N-type material to form the various parts of the dual-gate MESFET. In particular, a heavily-doped (N+) GaAs section 54 forms the source 12, wherein the source ohmic metal 32 resides on the GaAs portion 54. Moving left to right, a lightly doped (N−) GaAs portion 56 resides under the first gate metal section 44, which forms the first gate 16. A heavily doped (N+) GaAs portion 58 forms the inner SD node 20. Another lightly doped (N−) GaAs portion 60 resides under the second gate metal section 46, which forms the second gate 18. Finally, another heavily doped (N+) GaAs portion 62 forms the drain 14. The drain ohmic metal 38 resides on the GaAs portion 62.
In each of these transistor structures 10 of FIGS. 4-6, the inner SD node 20 is raised above the level of the immediately surrounding substrate 22, which is defined herein to include a base substrate and any of the epitaxial layers residing thereon that are doped or otherwise manipulated to form a transistor. In many applications, the gate structures, such as the first gate 16 and the second gate 18, are elongated, and therefore the inner SD node 20 may also be elongated and may run between the adjacent gate structures. As such, there will be elongated recesses between each edge of the inner SD node 20 and an adjacent gate structure.
To increase the effective source and drain areas 12, 14 to increase power handling while minimizing the space required to implement a particular transistor architecture 10, meandering transistor architectures have been developed. One such configuration is illustrated in FIG. 7, wherein a fingered source structure 64 is interleaved with a fingered drain structure 66. Each of the respective source and drain structures 64, 66 will include a bus portion from which multiple fingers extend. The fingers of the fingered source structure 64 are interleaved with the fingers of the fingered drain structure 66 to create a meandering path therebetween. To form a dual-gate transistor structure such as that shown in FIG. 7, first and second meandering gate structures 68, 70 extend along the meandering path formed between the fingered source structure 64 and the fingered drain structure 66. The first and second meandering gate structures 68, 70 are substantially parallel to one another along the meandering path. The first and second meandering gate structures 68, 70 are generally configured not to make contact with each other or with any portion of the fingered source structure 64 or fingered drain structure 66. The first and second meandering gate structures 68, 70 may extend outside of the fingered source and drain structures 64, 66 to corresponding first and second gate contacts 72, 74.
Depending on the fabrication process, a segmented SD structure 75 may be formed along the meandering path between the fingered source and drain structures 64 and 66, and in particular, between the first and second meandering gate structures 68 and 70. Unfortunately, existing designs do not provide access to the segments of the SD structure 75 in a meandering transistor architecture. Thus, applications such as the antenna switch illustrated in FIG. 1 are not able to take advantage of the space efficiencies provided by multiple-gate transistor architectures, because the segmented SD structure 75 is not accessible for biasing.
Accordingly, there is a need for a multiple-gate transistor that has a meandering transistor architecture, where the meandering SD structure that resides between adjacent meandering gate structures is electrically accessible by associated circuitry.